Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Increases in storage density have been facilitated in various ways, including increasing the density of memory cells on a chip enabled by manufacturing developments, and transitioning from single-level flash memory cells to multi-level flash memory cells, so that two or more bits can be stored by each flash memory cell.
A drawback of increasing storage density is that the stored data is increasingly prone to being stored and/or read erroneously. An error control coding (ECC) engine is utilized to limit the number of uncorrectable errors that are introduced by electrical fluctuations, defects in the storage medium, operating conditions, device history, and/or write-read circuitry, etc.
Performance variability can be especially problematic when an interleaving scheme is used. Interleaving is generally employed to normalize the distribution of errors throughout a codeword or a set of codewords so that the quantity and distribution of errors falls within the error correcting capability of the ECC used to encode data into a set of one or more codewords. To that end, as an example, one interleaving scheme includes dividing a codeword into portions and assigning the codeword portions to respective memory devices in the memory system, so that each memory device stores a portion of the codeword. The result is that the average number of errors introduced by each memory device is spread over a set of codewords so that no one codeword is adversely affected by a particularly error-prone memory device disproportionately more than the other codewords. A drawback, however, is that such an interleaving scheme introduces the risk that one particularly error-prone memory device in the memory system can cause a catastrophic loss of data from multiple codewords. For example, the errors introduced in one portion of a codeword by one memory device may be so severe that the entire codeword is uncorrectable, irrespective of the performance of the other memory devices. If that one memory device has substantially the same impact on a set of codewords, large amounts of data may be irrecoverable because of the errors caused by the one memory device.